介绍了以多片ＤＳＰ和可编程器件可编程门阵列（ＦＰＧＡ）相结合构成的雷达检测录取单元，给出了系统的软件流程图．分析了实时处理的速度。用此方法设计的雷达检测录取器具有体积小、可靠性高、通用性强的优点。

A radar target detector unit based on multi-DSP combined with FPGA waspresented,the software flow chart for system work is given and the demand speed for real-timeprocess was estimated. The radar target detector designed by this method has the advantages ofsmall size,high reliability and general compatibility.

TN957.51