研究了基于多片DSP和FPGA、CPLD等可编程器件的雷达信号处理机的设计方法，在对雷达信号处理算法与体系结构的映射进行讨论的基础上，以ADSP21161和V2 FPGA以及XC9500系列CPLD为实例，介绍了信号处理机的具体设计与实现，该结构实时信号处理能力强，具有较强的通用性。

The design and implementation of a new signal processing architecture in radar based on multi-DSP, FPGA and CPLD were studied in this paper. Some rules and methods for algorithm and architecture mapping were presented and discussed. Multi ADSP-21161Ns and V2 FPGA, CPLD were taken as examples to describe the details during design and implementation. This system has proved to be a real-time one and could be applied to many applications in radar systems. [

TN957.51