数字下变频的FPGA实现通常都是基于查表的方法，为了达到高精度要求，常常需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的数字下变频实现方案，可有效地节省FPGA的硬件资源，提高运算速度。文章最后给出了该方案的精度分析和实验的仿真结果。

The common approach to implement DDC (Digital Down Conversion) on FPGA is based on a look-up table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of DDC on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. Finally, a quantization error analysis and simulation results are presented.

TN957.51