宽带、细步进频综的设计是一项具有挑战性的课题。利用高性能直接数字合成器（DDS）驱动锁相环路，可以在很大程度上降低环路设计的难度，并实现普通模拟方法难以实现的宽带细步进性能。文中重点介绍了AD9956的参考源实现，通过测试结果分析了DDS杂散和相噪特性，提出了优化和改进的方法。

The design of wideband high resolution frequency synthesizer is challenging. A DDS-dfiven PLL would alleviate the complexity of the loop design, and in the mean time obtain a competitive performance compared to traditional analog methods. In this paper, the realization of the reference source is discussed in detail, where AD9956 DDS chip was presented and analyzed, optimization solutions were given for better spurious performance.

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