在高速信号处理中，特别是在大时宽带宽积条件下，高速雷达信号的数字正交采样和脉冲压缩包含大量的乘加运算，运算量非常大，使用DSP芯片实现需多片处理完成，使系统的工作延迟大、成本高、功耗大、调试困难。文中采用CSD（Canonic Signed—Digital）算法的思想，实现数字正交采样和脉冲压缩滤波器算法优化，可显著降低运算量，使用可编程逻辑器件迅速快捷完成系统的硬件设计，并用Ahera公司的FPGA芯片进行了验证，最后给出了结果比较和分析。

The computation hurden of the filter of the quadrature sampling and pulse compression is huge in high-speed signal processing, especially for big time-band width product. Using DSP chip brings about lower frequency, bigdelay, high expense, big power consumption, difficult debugging, and difficulty to satisfy guideline. Realizing optimized filter of the quadrature sampling and pulse compression with FPGA in CSD can reduee burden of computation significantly, and we can use FPGA to realize design of hardware quickly and easily, in addition, realizing the method by use of FPGA produced hy Ahera company.

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