在搭建数字接收机之前可以通过利用仿真软件先进设计系统建立算法的顶层模型,以便指导实现接收机的各种功 能和指标。根据上述思路,文中设计了16通道数字接收机,集成在160 mm×233.35 mm 的印刷电路板上。使用120 MHz 时钟对75 MHz中频信号采样,再通过数字下变频器将频率搬移到零频并分为I、Q两个正交的通道。每个通道的瞬时动 态范围可以达到75 dB,通过与仿真结果相比较,数字接收机的性能达到预期。

Before building a digital receiver, a simulation using advanced design system can get the functions and performances to tutor the top designing. Then, the digital receiver consisting of 16 channels is built on a board (160 mm×233.35 mm). We demonstrate the 75 MHz anlalog signal is sampled by 120 MHz clock frequency. Subsequently, the DDC (digital down-converter ) converters the central frequency to 0 Hz, and I/ Q channels are set up. The instantaneous dynamic range of input is 75 dB. Compare with the results of the simulations, the performance of the digital receiver is eligible.