提出了一种可变分数延时宽带数字滤波器的优化设计方法,该方法首先采用内插的方法提高采样率,降低信号的归 一化带,再采用Farrow结构来实现分数延时,通过抽取,恢复信号的初始采样率。其实现形式采用基于多相滤波的级联结 构,使得内插和抽取相互抵消,降低滤波器的阶数,提高运算效率。采用基于FPGA的并行分布式算法,设计利用了器件 的结构特点以及与器件特性独立的2种方法,在时域实现了高速、高阶的宽带分数延时滤波器,并在Altera Stratix FPGA上 进行了仿真验证,最高工作频率分别为184 MHz 和119 MHz。

An optimization design method of wide-bandwidth fractional delay filter(FDF) is proposed in this paper. A two times oversampled input signal is produced , halfband limited and then passed through a variable FDF, which is designed using the farrow structure. The resulting signal is then decimated by two in order to revert to the original sampling frequency. A polyphase structure provides an efficient implementation of the filter. Using the parallel distributed arithmetic based on FPGA, two methods then, one of which is device dependent while the other is device independent ,are designed to implement the FDF. The maximum operating frequencies of 184 MHz and 119 MHz have been achieved for the two methods when they are implemented in Altera Stratix FPGA.

总装预研基金资助项目