采用直接数字频率合成激励锁相环方案,基于现场可编程门阵列串行高速控制方式，设计并实现了一种低杂散、低相位噪声的C波段雷达跳频频率源。通过对有源环路滤波器参数和印制电路板的优化设计，使相位噪声和杂散等关键指标得到了极大改善。对系统设计方案、m序列发生器、跳频时间和相位噪声模型做了详细的理论分析和估算。测试结果表明：在7.5 GHz处,相位噪声≤-100 dBc/Hz@100 kHz，杂散电平≤-65 dBc，跳频时间≤10 μs，输出功率>10 dBm,实测结果满足产品的设计指标要求。

Based on a FPGA unit which is used to control high speed serial mode, a C band frequency hopping source is implemented with direct digital synthesis and phase locked loop technology. It has some advantages such as low spurs, low phase noise, and fast hopping time. The performances of phase noise and spurs are improved by optimizing printed circuit board and the active loop filter parameters. The scheme design, m sequence generator, hopping time and phase noise module are analyzed in detail. The testing results show that phase noise is than -100 dBc/Hz @ 100 kHz offset frequency, spurious output is no more than -65 dBc, hopping time is no more than 10 us, and output power is greater than 10 dBm at 7.5 GHz. The experimental results meet the requirements of product design index.

TN74

四川省教育厅项目;四川省科技支撑项目