为满足现代雷达的高性能应用需求,文中提出并设计了一种可重构专用处理(RASP)架构。其采用非规则化微结构和混合重构策略,有效提升了并行流水计算的性能;通过兵乓处理机制掩盖DDR读写时间,充分发挥了运算资源的效率。RASP作为硬件加速核嵌入华睿2号DSP芯片并于TSMC 40 nm工艺下完成流片。测试结果显示,RASP完成1 K(1 024)点FFT的运算时间为2.57μs,处理效率高达42%,相比于NoC、MorphoSys、C6678、T4240等处理器,性能提升至1. 9~30倍,效率达到1.25~4 倍。

To meet the demands of high performance applications in modern radar, RASP architecture is presented in this paper. Through anomalistic microstructure and mixed reconfigurable strategy, the performance of parallel-pipeline compute improves in effect. With ping-pang processing method which conceals DDR read-write time, RASP also gives full play to the efficiency of computing resources. As a co-processor, RASP is tapped out and integrated in the DSP chip Huarui-2 with TSMC 40 nm. The test results demonstrate that 1 K FFT calculating only needs 2.57μs. The processing efficiency is as high as 42%. The performance is about 1.9~30 times and the efficiency is about 1.25~4 times as other FFT processors like NoC, MorphoSys, C6678, T4240, et al.

TN957