为解决雷达、电子对抗等高性能计算应用中的存储访问带宽瓶颈,文中设计了一种多通道交织的存储架构,通过存储通道间的地址交织映射和集中式调度器的拆分与重组,实现了多个物理存储通道的并发访问,成倍提高了访存带宽,并具有良好的可配置和可扩展特性。该设计充分利用市场现有成熟的单通道控制器技术,经济高效。为评估性能,以4通道存储系统为例,建立了周期精确的RTL模型及其仿真验证环境。测试结果显示,交织粒度在64 B~512 B内系统获得最优性能,该性能是目前广泛采用的独立多通道存储架构性能的约4倍。

To address the memory access bottleneck of high performance computing (HPC) such as radar and electronic warfare, a multi-channel memory architecture with address interleaving is proposed in this paper. By address interleaving and centralized scheduling, parallel access to multiple memory channels is realized and the memory bandwidth is significantly improved. The proposed architecture is highly configurable and scalable. It is also extremely economical by taking full advantage of existing mature single-channel memory controller technology. To evaluation the performance, a cycle accurate register transfer level (RTL) model is developed and configured as a 4-channel memory system. Experiments results show that the interleaving sizes between 64 Bytes and 512 Bytes are optimal, and the corresponding performance is about four times compared to the independent multi-channel architecture which is widely used at present.

TP971