数字抽取滤波器是Sigma-Delta(Σ-Δ)模数转换器(ADC)的重要组成部分,它负责撞鄄驻调制器输出信号的滤波和抽取。文中设计的数字抽取滤波器由级联积分梳状(CIC)滤波器、CIC补偿滤波器和半带滤波器组成。首先,介绍Σ-Δ ADC原理;然后,讨论数字抽取滤波器的原理及实现;接着,分别从MATLAB和Verilog实现验证抽取滤波器的功能;最后,通过测试实际芯片验证数字抽取滤波器的功能和性能,满足设计要求。

Digital decimation filter is an important part of the Sigma-Delta (Σ-Δ) analog digital converter(ADC), which is responsible for filtering and decimating modulator output signal. This design of a digital decimation filter is constituted by the cascode integrated-comb(CIC) filter、CIC compensation filter and half band filter, First, Σ-Δ ADC principle is introduced; then, the digital decimation filter principle and realization is discussed; later, the funiction of the decimation filter is achieved respectively by MATLAB and Verilog; finally, the actual chip is tested and verificated, and the function and performance of the chip meet the requirements.

TN713