以现场可编程门阵列为平台,提出一种通用定时设计架构,即软件化定时设计方法。它将定时程序划分为软件程序和硬件逻辑两部分,其中硬件逻辑采用定时产生子模块与合成模块实现通用化架构,软件程序为每个子定时配置位置与合成参数,从而实现复杂定时时序的产生。该方法可灵活、快捷调整定时时序,有效提升定时设计与调试效率。

Based on field programmable gate array (FPGA), a general framework named software defined timer design approach is proposed. It partitions the timer program into two separate parts, of which the hardware logic is designed to be a general structure consist of sub-timer module and combiner module, and the software program provides count and combination parameters for each sub-timer. The proposed timer design approach is flexible and easy to modify the timing, thus it can significantly improve the efficiency of system design and integration process.

TN958