针阵列雷达矩阵运算中的两种最具有代表性的矩阵求逆与线性方程组求解进行详细分析与方法实现。针对复杂的大数据量的矩阵运算,采用传统中央处理器(CPU)串行计算方式会大量引起的消耗大量CPU资源与时间的问题,提出了一种采用CPU+现场可编程门阵列(FPGA)硬件加速实现异构计算的方法。该方法为算法移植到FPGA芯片实现,针对循环迭代的串行计算,利用FPGA丰富的逻辑资源实现并行执行,利用FPGA内置的寄存器与随机存取存储器(RAM)资源实现大量的中间变量的缓存,利用FPGA内置的硬核数字信号处理器(DSP)资源实现数学计算加速,从而达到节约计算时间,节省CPU资源消耗的目的。开展基于FPGA硬件实现的高性能矩阵并行计算技术的研究,以满足高性能矩阵计算的高维、实时性和高精度等技术指标。实验结果表明采用基于CPU+FPGA硬件芯片的异构计算的时间小于原本单纯采用CPU计算的时间,且随着矩阵维度的增加即计算的复杂性与计算量的增加差异越明显。

In this paper, the two most representative methods of matrix inversion and system of linear equations in array radar matrix operation are analyzed and implemented in detail. Aiming at the complex matrix operation of Big data, in order to solve the problem that the traditional Central Processing Unit (CPU) serial computing mode will consume a lot of CPU resources and time,a method of heterogeneous computing using CPU + Field Programmable Gate Array (FPGA) hardware acceleration is proposed. Utilizing FPGA's rich logical resources to achieve parallel execution in serial computing for loop iteration; Using FPGA built-in registers and Random-Access Memory (RAM) resources to achieve a large number of intermediate variable cache; Utilizing the hard core digital signal processor (DSP) resources built into FPGA to accelerate mathematical calculations, thereby achieving the goal of saving computation time and CPU resource consumption. Conduct research on high-performance matrix parallel computing technology based on FPGA hardware implementation to meet the technical indicators of high-dimensional, real-time, and high-precision high-performance matrix computing. The results of experiment show that the time of Heterogeneous computing based on CPU+FPGA hardware chips is less than that of the original CPU computing, and the difference between the complexity of computing and the amount of computing is more obvious with the increase of matrix dimensions.

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