晶圆级封装技术能够大幅压缩前端收发组件的体积和重量,实现有源相控阵雷达的小型化,也带来诸如热管理、通道隔离、信号串扰、可返修性、可测试性等方面的技术挑战。由于引入了较多的先进工艺步骤和复杂的封装架构,如何对其进行测试以保证成品率、降低成本成为行业关注的技术难题。文中介绍了毫米波晶圆级异构集成封装工艺技术,并针对典型晶圆级封装组件的集成方案和测试流程对测试技术需求和面临的技术挑战进行了深入分析,对产品测试过程中涉及的晶圆级探针分层测试、治具测试和空口(OTA)测试三个关键技术进行梳理和总结,对后续射频晶圆级3D封装组件/模块的测试具有重要的借鉴和参考价值。

Wafer level packaging (WLP) technology can significantly compress the volume and weight of the front-end transceiver module, realizing the miniaturization of active phased array radar. However, it also brings great challenges, such as heat management, channel isolation, signal cross-talk and adaptability of repairing and testing. Due to the introduction of more process steps and complex package architecture, how to test wafer level packaging modules to ensure yield and reduce testing costs has become an important technical issue. In this paper, the wafer level heterogeneous integration technology in millimeter-wave is summarized. Besides, the testing requirements and technical challenges, along with some integration solutions and testing process of typical products are deeply discussed. The existing key technologies are sorted out from three aspects: wafer level testing with probe station, socket testing and over the air (OTA) testing. It can provide some valuable references for the construction of radio frequency wafer level 3D packaging modules.

TN957. 3